1. Field of the Invention
The present invention relates to a semiconductor storage device and a manufacturing method thereof, and more particularly to a semiconductor storage device including a plurality of semiconductor element devices having different functions and a manufacturing method thereof.
2. Description of the Related Art
In a semiconductor storage device, e.g., a flash memory of a NAND or NOR type, each semiconductor element device in the semiconductor storage device has been further miniaturized to realize high integration. However, when miniaturization advances, it has been perceived that a short channel effect of a memory cell transistor that stores information becomes considerable and OFF characteristics are degraded.
As one of methods for solving the short channel effect, there is a semiconductor device that uses a silicon-on-insulator (SOI) substrate having a thin semiconductor layer, e.g., a silicon layer, provided on an insulator. However, the crystallinity of the semiconductor layer provided on the insulator may inferior to the crystallinity of a bulk substrate depending on a manufacturing method thereof. Therefore, in a non-volatile semiconductor storage device such as a NAND flash memory, a peripheral circuit including a high voltage transistor is desired to be disposed on a bulk substrate having the excellent crystallinity.
A semiconductor device using a partial SOI substrate, which partly includes SOI regions, is disclosed in, e.g., JP-A 2003-203967 (KOKAI). The partial SOI substrate disclosed in this patent document uses a commercially available SOI substrate as a starting material. An SOI layer and a buried insulator, e.g., a buried oxide (BOX) film, are partially removed to expose a silicon substrate surface in order to form a non-SOI region. Then, an epitaxial silicon layer is formed on the exposed silicon substrate to fabricate the partial SOI substrate including an SOI region and the non-SOI region. Then, for example, a logic circuit is formed in the SOI region, and a DRAM and a sense amplifier circuit are formed in the non-SOI region. This technology uses the commercially available SOI substrate as a starting material and hence its cost is high as compared with a case where a bulk silicon substrate is used as a starting material.
Another technology of fabricating a partial SOI substrate without using a commercially available SOI substrate is disclosed in a specification of U.S. Patent Application Laid-open No. 2006/0048702. The technology disclosed in the patent document uses a single crystal region provided in an insulator as a seed crystal. According to this technology, a first epitaxial layer protruding above a surface of the insulator is first provided on the seed crystal. Furthermore, an amorphous silicon layer that covers the first epitaxial layer is deposited on the entire surface, and solid phase epitaxial growth is performed to case a lateral epitaxial growth with the first epitaxial layer being used as a seed to form a second epitaxial layer on the insulator, thereby fabricating the SOI substrate. Subsequently, a single crystal portion protruding on the first epitaxial layer is removed by, e.g., reactive ion etching (RIE), to be planarized.